| 摘要 |
PURPOSE:To satisfactorily keep a charging characteristic and improve a charge retention by a method wherein a pulse voltage lagging behind a gate driving pulse is generated to be applied to a drain at a location apart from the charge retention means without directly applying a high voltage to the drain of a charging FET. CONSTITUTION:The lagging pulse phiD is applied to the drain of the FET T1 of the enhancement type by a charging clock phi of a gate. A phase relation between the phi and the phiD is that a voltage difference at the same time is made over a threshold voltage Vth of the T1, and the final voltage ''1'' of the phiD is satisfied with VDD- Vth if the phi equals to VDD, and even with over VDD-Vth if a conductance of the T1 is selected in order that a decoder output V0 is charged up to approximately VDD-Vth when the formula phi=VDD-Vth is reached. With this construcdion, the T1 always actuates in a triode region to make a minority carrier caused by the collision ionization to be restrained, the charge retention characteristic to be improved, the decoder ''1'' voltage to be charged as VDD-Vth and the charging characteritic to be improved as well. |
