| 摘要 |
PURPOSE:To improve the efficiency of use of memories, by providing the 1st, the 2nd and the 3rd numerical information signal generating circuit, and outputting a write address signal in response to the result of summation of numerals of each output of the 1st, the 2nd, and the 3rd circuits and a readout signal with the result of summation of the 1st and the 2nd circuits. CONSTITUTION:At the readout mode, the output of a relative address generating circuit 8 as the 1st numeral information generating circuit and of an absolute address generating circuit 12 as the 2nd numeral information generating circuit is added at a full adder and a signal in response to the readout address is outputted from a full adder 13. At the write mode, the outputs of the circuits 8, 12 and of a presettable up/down counter 15 as the 3rd numerical information generating circuit are full-added and a signal in response to the write address signal is outputted from the full adder 13. Thus, the detection of the generation of overflow/underflow of the memory and the amount of jitter margin is made easy, to improve the efficiency of use of memory. |
