| 摘要 |
PURPOSE:To reduce the number of hardwares for checking significant digits to shorten the processing time and to simplify the processing procedure by detecting a significant digit of only a multiplier and using the whole digits of a multiplicand for addition. CONSTITUTION:The lowermost digit of a multiplier from an OP2 register 102 is taken out to a multiplier decrement counter 107, and when the vaule of the lowermost digit is a significant value of 1-9, the multiplicand stored in an OP1 register 101L is added to the high-order eight digits and the low-order eight digits of an OP1 register 101U respectively by an adder 103 by the number of times conforming to the contents of said digit of the multiplier. After completion of the processing for one digit of the multiplier, the multiplicand stored in the OP1 register 101L is shifted carried by one digit by a shift circuit 105 and stored in the OP1 register 101L. Subsequently the succeeding digit of the multiplier is taken out from the OP2 register 102 and said processing is repeated. |
