| 摘要 |
<p>A special character sequence detection circuit arrangement for use with a central exchange of a time multiplex digital telecommunications system connecting data terminals evaluates an established set of data characters. This set includes special characters which, when sent out by the same data terminal repetitively and a predetermined number of times, are recognized and evaluated for triggering a corresponding control process. The circuit arrangement is provided with a random access memory (306) having memory locations each associated with a respective one of the data terminals for storing a previous character code and a previous count number. A first read-only memory (302) receives the currently transmitted data character and assigns an individual character code to each special character. A second read-only memory (304) programmed to derive a validated character code and an incremented count number from a combination of this individual character code, the previous character code and the previous count number. The generated information is fed back to the random access memory. A sequence is detected in dependence upon an overflow of the maximum count number and a detect control signal is provided by the second read-only memory.</p> |
