发明名称 DIGITAL MULTIPLEX ECHO SUPPRESSOR
摘要 PURPOSE:To apply the titled echo suppressor to a line of asynchronous transmission and reception, by forming a tansmission suppression circuit and a reception loss circuit incorporatedly, decreasing the number of signals to be compared, and providing both functions of full/half echo suppressors. CONSTITUTION:In the operation of the half mode with a mode switching signal 24 at first, an integrator 22 accumulates the information only from a comparator 14, the accumulated output is given to a control circuit 23, and after a prescribed operation residual time, the transmission suppression loss of a suppression reception loss circuit 7 (at transmission side) and the reception loss of a suppression reception loss circuit 8 (at reception side) are controlled. In this case, the reception loss of the circuit 7 and the transmission suppression loss of the circuit 8 are brought to the through-state (zero loss), allowing to form a conventional half echo suppressor. In the full mode operation with an external mode switching signal 24, the suppression and reception loss of the circuits 7 and 8 are made to zero through the control of the circuit 23 at no communicating state.
申请公布号 JPS58138131(A) 申请公布日期 1983.08.16
申请号 JP19820019653 申请日期 1982.02.12
申请人 NIPPON DENKI KK 发明人 FURUYA YOSHIJI;FUKUSHI YUUZOU
分类号 H04B3/20;(IPC1-7):04B3/20 主分类号 H04B3/20
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