| 摘要 |
PURPOSE:To attain small sized encoder and to increase the amount data processed at a time, by using a storage circuit for the operation of time axis in common, using an RAM performing the n-th time axis operation and applying the (n+1)-th time axis operation. CONSTITUTION:Input data W1, W2-'W8 from an input terminal IN are written in the RAM 11 with a write signal R/W outputted from a timing signal generating circuit 13. A write address is outputted to the RAM 11 from an address generating circuit 12 and a selection circuit 17 selects the input side. Further, data W1', W2'-,W8' subject to the 1st time axis operation are fetched in a latch circuit 14 at a signal FDR from a timing signal generating circuit 13, and data W1'', W2''-,W8'' subject to the 1st and the 2nd time axis operation are fetched to a latch circuit 15 with a signal NDR from the circuit 13. |
