发明名称 CLOCK PULSE GENERATING CIRCUIT IN PCM SIGNAL RECEIVER
摘要 <p>PURPOSE:To generate clock pulses having a number in following to the fluctuation of the pulse width of the region of ''1'' or ''0'' of a PCM signal, by generating a prescribed number of clock pulses at each region of ''1'' or ''0'' of the PCM signal. CONSTITUTION:The clock pluses (gs) is generated sequentially at the 2nd, 6th, 10th, as the pulse number of a reference signal (b) from the generation of a differentiation pulse (d) as clearly shown in figure (e.g., a clock pulse g1 is generated at the 2nd location in terms of the reference signal (b) from the generation of the differentiation pulse, and clock pulses g2, g3 are generated at the 6th and 10th respectively). Thus, the number of generated clock pulses (gs) is ''0'' when the pulse width of the consecutive ''1'' or ''0'' region of the PCM signal (a) is ''0'' or ''1'' in terms of the number of pulses of the reference signal (b), ''1'' when ''2''-''5'', and ''2'' when ''6''-''9'', which is the number so as to absorb the fluctuation of the pulse width of the region of the PCM signal (a).</p>
申请公布号 JPS58138145(A) 申请公布日期 1983.08.16
申请号 JP19820020299 申请日期 1982.02.10
申请人 SHARP KK 发明人 NISHIDA TAKASHI
分类号 H03K5/00;H04L7/02;H04L7/027 主分类号 H03K5/00
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