发明名称 INSULATED GATE SEMICONDUCTOR DEVICE
摘要 PURPOSE:To improve disruptive strength in case of latching of L load by forming a deep P<+> type well having high concentration by one part except the channel section of the P type well of a vertical MOSFET. CONSTITUTION:The deep P<+> type wells 7 having high concentration are formed by one parts except the channel sections of the P type wells 3 of the vertical MOSFET. Surface concentration shall be at least 1X10<17>atoms/cm<3> or more in the concentration of the P<+> type wells 7. Accordingly, the device does not function as a parasitic bipolar transistor by short-circuiting the base and emitter of a bipolar NPN transistor and lowering base resistance, and breakdown voltage BVDSS is increased, thus improving the dielectric resistance of the L load.
申请公布号 JPS58137254(A) 申请公布日期 1983.08.15
申请号 JP19820018746 申请日期 1982.02.10
申请人 HITACHI SEISAKUSHO KK 发明人 ASHIKAWA KAZUTOSHI;ITOU MITSUO;IIJIMA TETSUO;KATOU HIDEAKI;OKABE TAKEAKI
分类号 H01L29/10;H01L29/78 主分类号 H01L29/10
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