发明名称 COMMUNICATION SYSTEM BETWEEN PROCESSORS
摘要 PURPOSE:To attain the reduction of total cost and to minimize the increase in signal lines, by providing the same input and output interface to a master unit, in a system in which memories and processors are connected on a common bus. CONSTITUTION:In a system in which a main storage device 1 and plural processor units 3-5 are connected on a common bus 2, the processor unit for controlling an IO is defined as the master unit 3, and the same interface 7 as input and output interfaces 8, 9 is provided between the master unit 3 and the other slave units 4, 5, and a channel for the communication between processors is formed via the interface 7, then the communication between the processors does not give hindrance for the data transfer on the common bus.
申请公布号 JPS58137026(A) 申请公布日期 1983.08.15
申请号 JP19820019173 申请日期 1982.02.09
申请人 FUJITSU KK 发明人 BABA NOBUYUKI
分类号 G06F13/38;G06F13/36;G06F15/17 主分类号 G06F13/38
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