| 摘要 |
PURPOSE:To realize high integration density by providing the basic cells consisting of MOS transistors in the entire part of the desired regions of chip and by integrating the gate and wiring layers between basic cells with a common conductor layer including the area to be cut at the time of customizing. CONSTITUTION:An example where four pairs of CMOS circuits using a common gate is used as a basic cell is considered. Said common gate is formed by a poly-silicon layer 44. The poly-silicon layer 44 is provided adequately with narrow sectins, namely the neck parts 44a, 44b. This neck parts are provided to the area where cutting is expected in vew of easily cutting the poly-silicon layer 44 at the time of customizing. An LSI is configurated by arranging many unit calls as explaiend above. Namely, the polysilicon layer 44 is cut at any part of the neck 44a, 44b and simultaneously a metal wiring layer is formed. Thereby, the desired logic circuit is finally obtained. A master slice LSI which has a high integration density and allows free change of wiring can be obtained. |
