| 摘要 |
PURPOSE:To reduce the delay due to conversion, by forming a waveform conversion circuit by using a signal delaying an input signal. CONSTITUTION:A delay signal generating circuit is formed by using n-set of delay circuits D1-Dn, and the logical circuit is formed by using an (n+1)-input NOR circuit. At the initial state t0, an input signal S0 is set to 0, delay signals S1-Sn are zero and 1 is outputted for an output signal DO of the NOR. At the operation timing t1, the signal S0 changes to 1, resulting in that the NOR output is inverted and the signal DO goes to 1. Further, the signals S1-Sn go from 0 to 1 with a delay for each delay time TD. At the timing t2, even if the signal S0 is changed to 0, the signal DO remains 0. Further, the signals S1-Sn go sequentially to 0 with a delay of the time TD, and when the Sn is finally 0, the signal DO goes to 1. Thus, the signal DO is converted into the pulse width of TO+n.TD (where; T0 is pulse width). In this circuit, since the delay time is required for only one stage of the NOR gate, the delay of conversion is reduced. |
