| 摘要 |
PURPOSE:To enable to make a level detecting circuit integrated with an MOS type semicondutor, by constituting the circuit by two voltage comparison circuits, a logical gate connected to the outputs thereof, two sampling switches, a sampling capacitor, and a hold capacitor. CONSTITUTION:An input signal VI is given to the non-inverted input of a voltage comparison circuit 5, while a hold capacitor voltage VR is given to the inverted input thereof. Meanwhile, a voltage -VR is given to the non-inverted input of a voltage comparison circuit 6, and the voltage of VI is given to the inverted input thereof. A logical sum is taken from outputs (a) and (b) of the voltage comparison circuits 5 and 6 by an OR gate 7. Accordingly, when VI is greater than VR, the output (a) of the voltage comparison circuit 5 is ''Hi'', while the output (b) of the voltage comparison circuit 6 is ''Lo'', and thus an output Vo of the OR gate 7 turns ''Hi''. When VI is less than -VR, the output (b) of the circuit 6 is ''Lo'' while the output (a) of the circuit 5 is ''Lo'', and thus the output Vo of the OR gate turns ''Hi''. Therefore, a circuit having such a constitution operates as a level detecting circuit whose output turns ''Hi'' when VI>VR and VI<VR. |
