发明名称 TESTING DEVICE FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To improve the processing capability of the titled device by executing tests while judging a test to be executed subsequently from the result of a preceding test and a mask information for each test when the operations of a plurality of ICs are tested in the execution of one test. CONSTITUTION:A system controller 1 starts testing from a test 1 of the highest- rank grade stored in a main memory 2. Measuring signals 6 in n sets, which can be given separately and independently, are given by a testing device 4 to n pieces of ICs 5 to be measured, output signals 7 numbering n are compared in the testing device 4 with an expected value generated from this device to determine the appropriateness of the ICs, and thereby the first test is completed. The system controller 1 puts masks on the results of measurement of all the tested ICs in the test currently performed, based on mask informations in this test which are stored in a mask information register 8, and cancels the mask informations according to the result of this masking, while determining a test to be performed subsequently. Based on this determination, a storage start address in the main memory 2 of this test is set in a program counter 9 from a test start address register 3, a test program is loaded from the main memory starting from the address set in the program counter 9, and the subsequent test is conducted.
申请公布号 JPS58135972(A) 申请公布日期 1983.08.12
申请号 JP19820019093 申请日期 1982.02.09
申请人 NIPPON DENKI KK 发明人 SAKAGAMI NAOTO
分类号 G01R31/26;G01R31/28;G01R31/316;H01L21/66 主分类号 G01R31/26
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