发明名称 LOGIC ANALYZER
摘要 PURPOSE:To perform a simultaneous display of many data and to measure quickly a prescribed logic signal, by displaying the logic signals of plural channels in the form of a set with the same symbol or character and in order of addresses of a storing means. CONSTITUTION:The logic signal words supplied from probes 10A, 10B, etc. of 8 channels, etc. are stored in a fetching storage circuit 14. Then a set of logic signals of 8 channels, etc. are written to an RAM 28 with each probe 10A- with the same character and in order of addresses after the process control carried out via a CPU 24, an ROM 26, etc. in response to the operation of a keyboard 30. The display of a CRT 34 is controlled via the RAM 28. Therefore a simultaneous display is performed for many data along with a desired display of the attribute of data, etc. Thus plural logic signals are quickly measured.
申请公布号 JPS58135463(A) 申请公布日期 1983.08.12
申请号 JP19820016545 申请日期 1982.02.04
申请人 SONII TEKUTORONIKUSU KK 发明人 YOKOGAWA HIDEMI
分类号 G01R13/28;G06F11/25 主分类号 G01R13/28
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