发明名称 |
SEMICONDUCTOR NON-VOLATILE MEMORY |
摘要 |
PURPOSE: To simplify the peripheral circuit of a semiconductor nonvolatile memory by a method wherein the voltage value impressed on a control gate electrode controlling the electrode potentials in the case of charging electrons to a floating gate electrode is equalized to the value of voltage impressed on an erasing electrode in the case of discharging electrons from the floating gate electrode. CONSTITUTION:A source region 2 and a drain region 3 both in N<+>region are formed on the surface of a P type semiconductor substrate 1 while a floating gate electrode 5 is provided through the intermediary of a gate oxide film 4. A control gate electrode 7 and an erasing electrode 9 are provided on the floating gate electrode 5 respectively through the intermediary of an insulating film 6 and a thin oxide film 8. The writing-in a semiconductor non-volatile memory depends on the voltage VFG of floating gate electrode 5 while the VFG is actually controlled by the voltage VCG of control gate electrode 7. In other words, the voltage VCG of control gate electrode specified to be VCG(>20V) is lowered down to be VCG=20V by increasing the capacity between the control gate electrode 5 and the floating gate electrode 7 so that said voltage VCG=20V may be equalized to the voltage of erasing electrode VEG=20V in case of erasing. Through these procedures, the peripheral circuits of semiconductor non- volatile memory can be simplified. |
申请公布号 |
JPS62254468(A) |
申请公布日期 |
1987.11.06 |
申请号 |
JP19860098821 |
申请日期 |
1986.04.28 |
申请人 |
SEIKO INSTR & ELECTRONICS LTD |
发明人 |
NAKANISHI AKISHIGE |
分类号 |
H01L21/8247;H01L27/105;H01L29/78;H01L29/788;H01L29/792 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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