发明名称 CLOCK REPRODUCING CIRCUIT
摘要 <p>Clock recovery arrangement suitable more specifically for an information transmission system using the TDMA principle in one transmission direction. A clock recovery arrangement (24, 13) employed in an information transmission system comprised of a central station (1) and remote stations (2, 3, 4, 5, . . . ). Each station has at least one transmitter circuit (11, 21, 23, 31, 41, 51) and one receiver circuit (12, 20, 22, 30, 40, 50). The information components are time-division muliplexed in the direction from the central station to the remote stations and are transmitted in accordance with the TDMA principle in the other direction. The clock signal H of the multiplex direction is used in the TDMA direction to set the frequency of a first phase-locked loop, while a second loop ensures a fast phase reset. This clock recovery arrangement constituted by this dual loop thus satisfies the requirements as regards precision and reduction of the residual jitter.</p>
申请公布号 JPS62256542(A) 申请公布日期 1987.11.09
申请号 JP19870096349 申请日期 1987.04.21
申请人 TELECOMMUN RADIOELECTR TELEPH <TRT> 发明人 JIYAN PIEERU BAREE
分类号 H04J3/06;H04L7/033 主分类号 H04J3/06
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