| 摘要 |
<p>PURPOSE:To hold a readout error within a specific value, by varying an input signal readout period according to signal order at every sampling period, and reading an input signal. CONSTITUTION:An FSK-modulated signal is demodulated by a demodulation part 28 into a digital signal 26, which is inputted to a detection part 29. Every time ''1'' of the input signal is received, the signal value read part 30 of the detection part 29 adds 1 to the counted value of a signal receiving circuit counting part 31 and when the sum reaches some value, the read part 30 reads the input signal to generate an output and also clears the counting part 31 to ''0''. The output of the read part 30 is ANDed with the output of the counting part 31 to generate a signal value output of the 1st order. Then, said operation is repeated to obtain signal values of the 2nd and succeeding order at corresponding output terminals of a signal order detection and display part 32. Those signal values are read as a readout value 27 to detect an original signal sequence and signal values.</p> |
