| 摘要 |
A process for fabricating an MOS electrically programmable memory array which includes a plurality of floating gate memory devices is disclosed. The process employs two layers of polysilicon, each of which are used to define a plurality of spaced-apart parallel lines with the lines of the other layer. Doped bit line regions are formed in the substrate in alignment with the first lines prior to the fabrication of the second lines. The first lines are etched in alignment with the second lines to define floating gates. Overlying metal lines (bit lines) are formed over the doped regions and coupled to the doped regions through periodic contacts. Substantially fewer contacts are required than in prior art arrays, permitting the fabrication of a higher density array. |
