| 摘要 |
The input/output lines (12, 14) of a semiconductor memory device are equilibrated up until the time of the read operation by a field effect transistor (24). The source and drain terminals of the transistor are connected to the input/output lines (12, 14), and the gate is controlled by an equilibration circuit (28). The equilibration circuit (28) includes a bootstrap capacitor (40) charged to the bootstrap voltage level by the self-timing action of the equilibration circuit (28) in response to a single precharge clock signal. Feedback from the output node (26) of the equilibration circuit (28) releases a Schmitt trigger circuit to allow the capacitor (40) to be pulled to the bootstrap level by the precharge clock signal. A pump circuit (30) maintains the voltage level at the output node (26) of the equilibration circuit (28) during periods of long inactivity between column address strobes.
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