发明名称 ARITHMETIC SEQUENCE DEVICE
摘要 PURPOSE:To obtain an arithmetic sequence device which minimizes the change of a program, by providing a circuit, which selects an optional auxiliary RAM in accordance with a selected ROM, in the output side of an auxiliary storage device selecting circuit which selects an optional ROM. CONSTITUTION:By the address signal of a CPU 1, a memory controlling unit MCU 17 selects a main storage device ROM 3, where programs and data related to the whole of plural units to be controlled are stored, and an RAM 2. The first auxiliary storage device selecting circuit 29 selects auxiliary ROMs 4-9, which are provided in accordance with units to be controlled and have the same addresses and store programs for corresponding units internally, by the address signal from the CPU 1. The second auxiliary storage device selecting circuit 36 is connected to the outut of the circuit 29. Since the circuit 36 selects an auxiliary ROM corresponding to the selected auxiliary ROM out of auxiliary RAMs 10-15 for storage of data of units corresponding to ROMs 4- 9 and a prescribed number of auxiliary RAMs other than this auxiliary RAM, the change of the program is reduced even if the controlling unit is changed.
申请公布号 JPS58132838(A) 申请公布日期 1983.08.08
申请号 JP19820018100 申请日期 1982.02.02
申请人 TOKYO SHIBAURA DENKI KK 发明人 OGURI JIROU
分类号 G05B19/05;G06F9/06;G06F9/26 主分类号 G05B19/05
代理机构 代理人
主权项
地址