发明名称 INTEGRATED CAPACITANCE
摘要 PURPOSE:To suppress change of capacitance within a wide positive and negative voltage range by providing, in addition to a second electrode in the same conductive type as an accumulation layer, a third electrode in the same conductivity type as an inversion layer in such a manner as in contact with said inversion layer and by using the second and third electrodes in common as the one electrode. CONSTITUTION:A thin silicon oxide layer 2 is formed on an N type substrate 1 and a first electrode 3 is then formed on said silicon oxide film 2, and a second electrode 5 of N<+> layer and a third electrode 6 of P type diffusion layer are provided in the substrate 1. Thereby, a P type inversion layer 4 generated when a negative voltage is applied to the electrode 3 is connected to the electrode 6 and thereby a capacitance CO is formed between the electrodes 3 and 6. Accordingly, a capacitance between the common electrode connecting the electrodes 5 and 6 and the electrode 3 changes in only a small amount.
申请公布号 JPS58132958(A) 申请公布日期 1983.08.08
申请号 JP19820015091 申请日期 1982.02.02
申请人 CITIZEN TOKEI KK 发明人 EBIHARA HEIHACHIROU
分类号 H01L27/04;H01L21/822;H01L29/94 主分类号 H01L27/04
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