| 摘要 |
PURPOSE:To save the hardware quantity and to decrease the time of multiplication, by dividing multipliers in response to the vector accuracy and applying the vector to one side of each multiplier with a shift register having the accuracy of matrix provided to the other side of each multiplier for the calculations of vector and matrix. CONSTITUTION:For the multiplication of (2X2) matrix pairs shown in the equation, a term A of the left side matrix is applied to one side parallel-series input type multipliers 3 (3a-3c) and at the same time a term E is added to a shift register 1 conected to the other side of the multiplier 3. Then the result of multiplication is stored in a register 2. Then terms B and G are applied to each multiplier 3 to be multiplied, and the result of this multiplication is added 4 to the contents of the register 2. Thus the 1st term (AE+BG) is calculated, and this calculation is repeated to perform a multiplication of (nXn) matrices. |
