| 摘要 |
A cross-under wiring construction comprises a semiconductor layer 5 forming a cross-under wiring, and an isolating semiconductor layer 3 formed in a semiconductor region 2, wherein a potential is applied to layer 3 so that operation of parasitic transistor (Qp) is suppressed, the construction is particularly for use in stacked I<2>L integrated circuits comprising blocks of I<2>L elements. Layers 3 may have potentials set to equal those of regions 2, but in the case of stacked I<2>L that requires a plurality of cross- under wiring layers formed close to each other in a P-type layer (3), it is desirable that the layers 3 are connected to a lower potential e.g. the regions 2 in the I<2>L block of a previous stage. A device of highly integrated form may be fabricated by ensuring that the wiring layers which extend from low potential driving I<2>L blocks to high potential driving I<2>L blocks do not use cross-under wiring, such wiring only being used within a single I<2>L block. The cross-under wiring may have significant resistance and may act as a resistance element. <IMAGE> |
