| 摘要 |
<p>A shift register (60) which can alter an effective bit length without any changes in the internal structure of the shift register (60). For that purpose, a transfer clock generator (71) which supplies a transfer clock to the shift register (60) is provided, this alters the obtained clock data of the transfer clock and the input state of the shift register. This shift register can be applied to a memory of an SPS structure or the like.</p> |
