发明名称 LOGICAL CIRCUIT
摘要 PURPOSE:To enable an operation of a short delay time even in case the capacity which is connected to an output is large or a TTL, etc. is connected, by driving the gate of a field effect transistor for power supply current with an output of a front stage. CONSTITUTION:The basic constitution of this example is equal to a conventional one, and the 2nd stage enclosed by a dotted line, i.e., an output stage inverter differs. That is, the gate of a current source FET provided at an output terminal is not grounded but connected to an output terminal of a front stage via a diode D44 for level shift. An MESFETQ37 is used for current source of the diode D44. When the gate of an FET-Q32 is set at level ''1'', the gate of an FET-Q32 is set at level ''1'' via the diode D44. Therefore the FET-Q36 can extract quickly the electric charge of above-mentioned gates even in case the FET group is connected in parallel to an output terminal.
申请公布号 JPS58130621(A) 申请公布日期 1983.08.04
申请号 JP19820012761 申请日期 1982.01.29
申请人 TOKYO SHIBAURA DENKI KK 发明人 SHIMIZU SHIYOUICHI
分类号 H03K19/0952;H03K19/017;H03K19/0944;H03K19/0956 主分类号 H03K19/0952
代理机构 代理人
主权项
地址