| 摘要 |
PURPOSE:To facilitate a design of a processing circuit system and to reduce the load, by giving the selecting right to the processing circuit system for an address which is necessary for an access of a receiving memory, writing reception data to the receiving memory with the clock of a transmission line system and reading the data with the clock of the processing circuit system to ensure an asynchronous operation. CONSTITUTION:A synchronizing circuit 1 secures clock synchronism with the clock of a transmission line system as well as frame synchronism by means of a frame synchronizing pattern F and transmits the clock and reception data, etc. to an S/P converting circuit and the clock to an address/clock generating circuit 5, respectively. The circuit 5 counts the clocks and feeds the address on a memory which is prescribed at positions of time slots 0-n to an address selecting circuit 7. While a processing circuit system 9 feeds a reception controlling signal (RTC) to an FF6 when the reception data must be fetched from a memory 8, feeds the address of the data which should be read out of the memory 8, gives an access to the memory 8 with the address and reads the desired data with own clock which is slower than the clock of the transmission line system. |
