发明名称 HOLDING SYSTEM OF FAULT INFORMATION
摘要 PURPOSE:To realize a means to hold assuredly the fault information although the power supply of a faulty device is cut off, by providing a means which receives the fault information given from the faulty device and then holds a fault display signal by means of a power supply which is independent of the faulty device. CONSTITUTION:The output of a delaying circuit 51 is fed to a terminal CL of a flip-flop 71 via a gate 16 in a conductive state. Therefore the flip-flop 71 via a gate 16 in a conductive state. Therefore the flip-flop 71 is set on the basis of the fault information (a) which is fed to a terminal D and then delivers the held fault information (b) through a terminal Q. The information (b) energizes a held fault information display 91 via a driver 81 and is also fed to a terminal S of a flip-flop 120 via a gate 10 and a delaying circuit 110 which has about 200mm. delay time. Thus the flip-flop 120 is set. As a result, gates 6l-6n are blocked by the output supplied from the terminal Q of the flip-flop 120 and after a delay time. Then the setting due to the fault information produced thereafter is prevented for flip-flops 7l-7n.
申请公布号 JPS58130661(A) 申请公布日期 1983.08.04
申请号 JP19820012995 申请日期 1982.01.29
申请人 FUJITSU KK 发明人 IGI YOUZOU;UCHIDA YUKIO
分类号 H04M3/22;G06F11/34;H04M3/08 主分类号 H04M3/22
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