DATA PROCESSING SYSTEM FOR INTERFACING A MAIN STORE WITH A CONTROL SECTRON AND A DATA PROCESSING SECTION

摘要

This invention relates to apparatus for interfacing a storage memory with a central processing unit.
Improved efficiency in the operation of a computer system is achieved by interface logic that control the operating rate of a central processing unit 14 to be compatible with the slower operating rate of main memory 12. Microinstructions are decoded and interlock latches are generated to provide a main store interface holdoff signal that is applied to holdoff latch logic. Normally, the holdoff latch logic provides load control signals to sequence the operating cycle of the central processing unit. Under certain identified microinstruction conditions, an interlock latch is generated and the load control signals are not output from the holdoff logic, thereby inhibiting the sequencing operation of the central processing unit. Interlock latches that are generated includes a register-in-use interlock and an invalid data interlock from each register that is used to fetch data from and store data into main memory.