| 摘要 |
<p>In the frequency control mode, a switch (23) is ON. A power difference (AP) is fed back to an adder (18) through a limiter (21) and is compared with an output from a power setter (9a). A difference signal (Pdp) from the adder (18) is supplied to an adder (19) to obtain a difference (AP) with detected power (Pd). By the feedback loop, the preset power (Pdp) is set to be substantially equal to the detected power (Pd). While the difference (AP) is greater than a predetermined value, an output from a level detector (22) is at logic level "0". Even if a mode switch instruction is received in this state, an AND gate (24) does not produce an output signal and the mode changing is not performed.</p> |
