| 摘要 |
PURPOSE:To eliminate a phase difference of an output signal due to mode selection, by providing a means which counts a start signal in common to a reference clock signal and a means which selects a counting end signal for a register set value. CONSTITUTION:The carry signal of a counter 3 is selected by logical circuits AND1 and AND3 according to a mode selection signal, and the start signal is inputted to a terminal CLR temporarily and then inputted to a reset FF; and a succeeding reference clock signal is inputted to a terminal CK and a signal from a terminal Q is inputted to a delay element group 4. Only one delay element group 4 is provided to obtain low-order value delay time width and one of set values by registers 2a and 2b is selected by a multiplexer 5 according to the mode selection signal for selecting the carry signal of the counter 3 previously and inputted to the delay element group 4. |
