| 摘要 |
A monolithic static memory cell has two cross-coupled inverters each comprised of a series connection of a field effect switching transistor and a load element designed as a field effect transistor. The field effect transistors forming the load elements have their channel resistances of different values. A gate insulating layer of one of the load element field effect transistors has its charge state altered, preferably by electron beam writing, so that a change in a threshold voltage of the one transistor results in a change of its channel resistance relative to the channel resistance of the other load element transistor if it was under before the selective altering, or vice-versa.
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