发明名称 INPUT AND OUTPUT CONTROLLER
摘要 PURPOSE:To reduce the overhead of a CPU by preparing a queue from a queue header table and a queue connecting table and setting a flip-flop to start an I/O instruction. CONSTITUTION:When the channel number of a channel controlling device CHC 3 is effective, the CHC 3 always receives an I/O instruction from the CPU, registers the instruction in an I/O instruction queue and sets an I/O instruction execution waiting flip-flop after preparing the queue. When each of channels 4-1- 4-N is made idle, the channel checks said flip-flop and when the flip-flop is set, generates an interruption to the CHC 3 to request the starting of execution. The CHC 3 removes I/O devices which are registered in the queue and enabled to execute the I/O instruction at present in sequence from the queue and executes the I/O instruction specified to the devices.
申请公布号 JPS58129627(A) 申请公布日期 1983.08.02
申请号 JP19820013486 申请日期 1982.01.29
申请人 NIPPON DENKI KK 发明人 SHIBATA YOSHIHISA
分类号 G06F13/12 主分类号 G06F13/12
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