| 摘要 |
PURPOSE:To attain a charge extraction test of all memories at a time independently of the number of decoders, by taking a potential of a control gate of all memory transistors (TRs) to a specified potential at information write or equivalent at the same time with a prescribed control signal. CONSTITUTION:At normal write-readout mode, a test control signal to a terminal 16 is made to ''L'' level and TRs 13-15 are kept nonconductive. At the extraction test, the signal to the terminal 16 is kept to ''H'' level to conductive the TRs 13-15, allowing to bring the potential of address signal input terminals 3-5 to ''L'' level forcedly. Thus, decoder TRs 6, 7, 8 of all decoders D are nonconductive, the output of all the decoders, i.e., the control gate of the memory TRs Q1, Q2 goes to ''H'' level, allowing to attain the charge extraction test for all the memories at a bundle. |
