发明名称 CONTROLLING OF DATA FLOW RATE
摘要 PURPOSE:To prevent the inflow of data exceeding the processing capacity, by monitoring the difference of the number of transfer rings to transmit and receive data by an identifier, when data comprising an identifier and a data are transmitted and received between two information processors. CONSTITUTION:When a data is transferred to an information processor 2 from an information processor 1, the processor 1 delivers a data comprising an identifier and a data to a line 101 as long as a data acceptable signal exists on a signal line 102 when a cue memory 100 has a data storing area having an FIFO function. This data is preserved at the memory 100 and then read out to a line 103. Then the identifier gives an access to the table memory 100, and a new identifier is read out to a data line 106. An increment monitor bit is applied to a signal line 114. Then a data identifier gives an access to a memory 120 when the data is transferred to the processor 1 from the processor 2 and then delivers a decrement monitor bit to a signal line 113. A counter 130 has an increment or decrement by the signals of signal lines 114 and 113 and then indicates the inhibition of reading through lines 117 and 109 in case the count value is larger than a fixed value of a register 150.
申请公布号 JPS58127249(A) 申请公布日期 1983.07.29
申请号 JP19820010309 申请日期 1982.01.26
申请人 NIPPON DENKI KK 发明人 TENMA TSUTOMU;IWASHITA MASAO
分类号 G06F9/38;G06F9/44;G06F15/16;G06F15/167;G06F15/177;G06F15/82 主分类号 G06F9/38
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