| 摘要 |
PURPOSE:To reduce the memory capacity used as a table, by obtaining the syndrome at each block from a plurality of partial syndromes obtained from a plurality of tables and correcting errors of information. CONSTITUTION:A shift register 2 shifts information from a terminal 1 with a clock pulse applied from a clock generator 4 and supplies it to a latch circuit 5. A synchronizing detector 3 detects the synchronism of the block and supplies the result to a reset terminal of a counter 6. The counter 6 divides in terms of frequency the clock pulse grom the generator 4 and supplies it to the latch circuit 5. The latch circuit holds the bits in one block applied from the shift register 2 every time the pulse is applied from the counter 6. Tables 8 and 9 formed in a memory 7 are indexed with high-order and low-order bits, respectively. The two partial syndromes thus obtained are inputted to an exclusive logical sum circuit for calculation, allowing to obtain the syndrome. |
