发明名称 PROCESSEUR DE MICROORDINATEUR
摘要 The processor for microcomputers according to the invention contains a fast memory (1), an arithmetic/logic unit (2), an interface (3), a microprogram control block (5), which are each connected to one another via an internal data bus (4) of the processor, and a processor status register (7). The processor also has a constant memory (10), a first and a second switching section (12 and 13, respectively) which are connected to the arithmetic/logic unit (2), a register (15), a source (7) for potentials (17) allocated to logic states, and a decoder (19). <IMAGE>
申请公布号 FR2520528(A1) 申请公布日期 1983.07.29
申请号 FR19820001340 申请日期 1982.01.28
申请人 DSHKHUNIAN VALERY 发明人
分类号 G06F7/495;G06F7/50;G06F15/78;(IPC1-7):G06F7/00 主分类号 G06F7/495
代理机构 代理人
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