CLOCK PHASE CONTROL METHOD FOR A DIGITAL DATA RECEIVING SYSTEM, PHASE RECOVERY CIRCUIT FOR CARRYING OUT THIS METHOD AND DIGITAL DATA RECEIVING SYSTEM COMPRISING THIS CIRCUIT

摘要

Method for controlling the phase of a decision circuit clock of a receiving system for digital data, according to which the frequencies above 1/T (T=data symbol period) are substantially eliminated, whereafter the phase deviation to be corrected is evaluated and the clock is shifted in accordance with this phase deviation, inclusive of its sign. An example of a circuit for using this method includes a lowpass filter circuit and an evaluation and phase shifting circuit for fixing the optimum decision instants of the decision circuit provided at the output of an adaptive filter.