发明名称 INTEGRATED CIRCUIT MEMORY
摘要 PURPOSE:To relieve a memory, the inside thereof has a defective bit, and to change the memory into an acceptable product by each setting up fuses among two terminals of a power supply and the input terminal of at least one address input means and also mounting a fuse between the input terminal and a joining pad. CONSTITUTION:A wiring node (a) is connected to line voltage Vcc, a ground and the pad 2 through high resistors R1, R2 and the fuses F1-F3 according to a prescribed method in an input stage 1 connected to an address terminal A10 at an uppermost level in the input terminal A0-A10 of a 2kX8 bit RAM illustrated. When a defect is discovered in some bit in which the uppermost level of address signals is specified as 1 by inspection, F3 and F1 are separated, the node (a) is brought to a ground level, and the uppermost level of the defective bit is changed into ''0'' from ''1''. Accordingly, one half in the memory is regarded as unusable and acceptables having 1kX8 bits, and the terminal A10 is expressed clearly as a non-connecting terminal. When the uppermost level of the defective bits is ''0'', F3 and F2 are separated, and the node (a) is brought to Vcc level ''1''. Accordingly, defectives can be relieved.
申请公布号 JPS58125846(A) 申请公布日期 1983.07.27
申请号 JP19820007629 申请日期 1982.01.22
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAMOTO AKIRA;MORIWAKI NOBUYUKI
分类号 G11C11/413;G11C29/00;G11C29/04;H01L21/82;H01L21/8242;H01L27/10 主分类号 G11C11/413
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