发明名称
摘要 PURPOSE:To eliminate the need for a large-capacity capacitor for integration which is necessary before by applying digital technology to a bridged tap equivalent circuit. CONSTITUTION:An input signal E0 containing an echo is led to an output terminal E1 through an analog adder 31 and a part of the signal is converted through OP amplifiers 32, 33, and 34 into digital signals E2-E4, which are led to a control part 35. Then, outputs E5 and E6 of this control part are applied to an up/ down counter 36 which accumulates the amounts of echo after one time slot and an up/down counter 37 which accumulates the amount of echo after two time slots. The outputs of both counters 36 and 37 are processed by addition or subtraction through a digital adder and subtracter 38 and then converted by a D/A converter 39 into an analog signal, which is smoothed by a smoothing circuit 40 and then supplied as an echo canceler signal to an adder 31.
申请公布号 JPS6253972(B2) 申请公布日期 1987.11.12
申请号 JP19830034814 申请日期 1983.03.03
申请人 NIPPON DENSHIN DENWA KK;NIPPON DENKI KK;FUJITSU KK;OKI DENKI KOGYO KK 发明人 ISHIKAWA MASAYUKI;KIMURA TADAKATSU;KURAISHI YOSHIAKI;TAKAHASHI YUTAKA;TSUDA TOSHITAKA;FUKAZAWA ATSUSHI
分类号 H04B3/06;H04B3/23 主分类号 H04B3/06
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