| 摘要 |
A digital output tapped filter is provided in which the filtered output signals are latched into a first latch circuit by the clock signal which clocks the serial shift register. Output signals are thereby held in the register during the time that new data values from the shift register are propagating through the adder tree and weighting function circuits. By the time that the clock signal again clocks the shift register, the filter output signal has settled, and can again be latched into the latch circuit. The signals at the output of the latch circuit are thus immunized from signal ripple. A second latch circuit is coupled to the output of the first latch circuit, and is clocked by the same clock signal as the first latch circuit. Consecutively produced filtered data words are thereby held in the latches, and the latched signals of N bits are applied to inputs of an N bit adder. The N bit adder produces an output signal of N+1 bits. The least significant bit of the adder output signal is discarded to produce an output signal of N bits with an improved signal-to-noise ratio. Since the latch circuits are latched by the same clock signal, and their output signals are applied to the same adder, substantially no ripple appears in the N bit output signal of the adder.
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