| 摘要 |
PURPOSE:To suppress an increase of a hardware quantity in case when the number of bits of a data has increased, by constituting a multiplying circuit for obtaining an error pattern, of a gate element, without using an ROM. CONSTITUTION:A parallel data of 8 bits for constituting an element A of a Galois field GF (2<8>) is supplied to a multiplier 109 of 8 bits, and also, an element B of the Galois field GF is converted to a serial data by a prallel-serial converter 108 and is supplied to the multiplier 109. For instance, when multiplication is executed by setting the element A and the element B to alpha<20> (=10110100) and alpha<9> (=00111010) respectively, an adder 97 obtains a prescribed output at every clock. Also, ''00110000'' of the eighth clock is alpha<29>, and this value is a value of an error pattern of AXB, which is a purpose. Said multiplier 109 is constituted of an AND gate 110, and the adder 97 is constituted of an exclusive OR 111. |
