| 摘要 |
PURPOSE:To provide the complementary type, high speed, high density, MOS semiconductor device wherein latch up is hard to occur, by making the impurity concentration at the side surface part and the bottom surface part of the first well higher than the impurity concentration of the part wherein a MOS transistor is formed in the first well. CONSTITUTION:P well regions 22 and 23 are formed in an N type silicon substrate 21. The P well 22 becomes a channel stopper which prevent the parasitic MOS effect at the periphery of the P channel MOS transistor without degrading characteristics of an N channel MOS transistor 24, by suppressing the P type impurity concentration lower than the P well. The resistance of the diffused layer of the P well can be reduced. Therefore the latch up becomes hard to occurs. Meanwhile, the channel stopper may be inserted if it is required to prevented the parasitic MOS effect of the P channel MOS transistor 25. When the concentration of the impurities of the N type silicon substrate 21 is high, the stopper is not required. |
