| 摘要 |
PURPOSE:To obtain high density integration, by using a plurality of Si gate MISFET having high degree of wiring freedom, thereby constituting serial parallel circuits in order to obtain desired logic readily and reducing the wiring area. CONSTITUTION:In the MISFET Q, P<+> type regions 161-164, which are connected to source and drain regions, are formed in a self-aligning mode with respect to an Si gate electrode 15. They are used as wirings. Therefore aluminum wirings as the wirings from the source and drain regions can be omitted. The wiring can be performed on either right side or left side of the gate. Furthermore, since the aluminum wirings from other regions can be freely formed through an insulating film on the MISFETQ, the wiring work for ICs becomes easy, and the restrictions for the layout becomes few. Since the P<+> type 161- 164 and source and drain regions 12 and 13 of the MISFETQ can be simultaneously formed with the implantation of other elements (e.g. D-PMOS and E- PMOS described above), any change in the existing manufacturing processes is not required. |
