| 摘要 |
PURPOSE:To reduce source resistance and gate capacitance and also obtain good high speed response characteristic by forming a stepped part having a slope to a stacked semiconductor layer and then forming a gate electrode which is in contact with inverse conductivity type impurity implantation layer formed on the titled plane. CONSTITUTION:An n-type InGaAsP active layer 12, a p-type InGaAsP current interceptive layer 13 and an n-type InP active layer 14 are caused to grow on a semi-insulative InP substrate 11, while a slope SL is generated by mesa etching, a part of p-type InGaAsP current interceptive layer 13 is converted to the n-type by ion implantation and moreover a p<+> type impurity implantation layer 15 is then formed. Next, a gate electrode film 16 consisting fo Au/Pt/Ti is formed by vacuum deposition, and when it is etched by ion etching, only the part being in contact with the slope SL remains. Therefore, it is used as a gate electrode 16G. Thereafter the impurity implantation layer 15 is etched with the gate electrode 16G as the mask and the source and drain electrodes 17S, 17D consisting of Au/Au Ge are formed by vacuum deposition where only the part just under the gate electrode 16G remains and other portion is removed.
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