| 摘要 |
PURPOSE:To improve the resolution and reliability of a position and speed detector with simple constitution by allowing a frequency multiplier which uses a PLL circuit to perform interpolation after modulating a frequency-divided carrier signal by a position detection signal, etc. CONSTITUTION:The periodic pattern of a scale 1 which moves relatively is read by a scale detector 2 to generate a digital detection signal regarding the position, etc. By this signal, a carrier of basic frequency fc frequency-divided to 1/N, etc., by a programmable frequency divider 4 is modulated through a modulator 5 to convert the position information into phase information. Then, the modulated signal is multiplied to an N-fold frequency N.fc by the frequency multiplier 6 using the PLL circuit to obtain a signal containing corresponding phase information after the interpolation; and the position is detected through a demodulating circuit 7 which makes a phase comparison between the output of the multiplier 6 and the reference signal of frequency N.fc, digital phase and speed information forming circuit 8, etc. This simple constitution including the easily- IC-implemented multiplier improve the resolution and reliability of the position and speed detector. |
