发明名称 INPUT OVERVOLTAGE PROTECTION CIRCUIT
摘要 <p>An input pad overvoltage protective circuit for integrated devices is disclosed. It enables both positive and negative polarity input signals be applied to a protected gate (14) of an FET (11). The protective circuit comprises a first resistor (12) coupled between an input pad (13) and the gate (14) and a current limiting second resistor (15) and diode (16) coupled between the pad and a reference potential.</p>
申请公布号 JPS58122695(A) 申请公布日期 1983.07.21
申请号 JP19820182214 申请日期 1982.10.19
申请人 INTERN BUSINESS MACHINES CORP 发明人 HAABAATO KAARU KUTSUKU;GEIRII DAGURASU GURAISU;CHIYUNGU HON RAMU
分类号 G11C17/00;G11C16/02;H01L27/02 主分类号 G11C17/00
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