| 摘要 |
PURPOSE:To reduce the component of a low frequency corresponding to the least significant bit of the converted value, by synthesizing shift register outputs of a plurality of stages in series connection selectively, generating a signal having a time component shorter than the period of a clock signal, and generating a signal having a pulse width not a multiple of the period of the clock signal. CONSTITUTION:When control signals 17, 18 are both logical value ''0'', a signal having a pulse width equal to that of a variable pulse width signal 14 is outputted. When the control signal 17 is logical value ''1'' and the control signal 18 is logical value ''0'', a signal having broader pulse width than a variable pulse width signal 14 is outputted while a clock signal 10 is logical value ''0''. When the signal 17 is logical value ''0'' and the signal 18 is logical value ''1'', the signal having broader pulse width than the signal 14 is outputted while a clock signal 10 is logical value ''1''. When both the signals 17, 18 are logical value ''1'', the signal hving broader pulse width than the signal 14 is outputted during one period of the clock signal 10. |
