| 摘要 |
PURPOSE:To improve the processing capacity, by installing an FIFO memory and a jump instruction processing device between a main storage device and a CPU and by accessing the CPU to the FIFO memory which is under conditions where the FIFO memory has no jump instruction. CONSTITUTION:When the content of a memory address register 31 becomes n+m, a jump processing device 3 accesses the n+m address of a main storage device, takes out an instruction In+m(J), and stores the instruction in an instruction register 32. When a jump instruction processing circuit 33 judges that the instruction In+m(J) is a jump instruction, the circuit 33 does not transfer the instruction In+m(J) to a first-in first-out memory 4, but takes out jump address data Dn+m+1 at (n+m+1) address by adding +1 to the content of the jump address register 31 and stores the data Dn+m+1 in a buffer register 34. The content of the memory address register 31 is rewritten in K which is a jumped address by using the content of the buffer register 34. |
