| 摘要 |
PURPOSE:To generate a sampling pulse which is free from an offect of variance of delay time and has a free external fine adjustment for the delay time, by forming a sampling pulse having a prescribed width, etc. with use of a 1/2 frequency divider, etc. CONSTITUTION:An original clock pulse phiIN supplied through a terminal J is inverted by an inverter 8 and then divided by a 1/2 frequency divider containing an FF, etc. through a delaying circuit 9 to be turned into transfer clock pulses phi1 and phi2 which are twice as much as the clock phiIN. At the same time, the pulse phi2 and the output of the inverter 8 are applied to produce a sampling pulse phiS through an AND gate 11. The pulse phiS has a width equal to that of the pulse phiIN of a repeating frequency of twice as much as pulses phi1 and phi2, a slower rise then the phi2 and a fall prior to the fall of the phiS and no effect of the variance of delay time. Furthermore the pulse phiS works in response to the duty ratio of the phiIN. As a result, the delay time can be finely adjusted from outside in an easy and free way. |
