| 摘要 |
PURPOSE:To minaturize a row decoder without increasing the current consumption, by providing the 3rd row decoder which responds to a timing signal in addition to the 1st and 2nd row decoders which select a block in which memory elements are connected in series to each other as well as the memory element. CONSTITUTION:The 2nd row decoder is formed with an NAND circuit containing p transistors TR38, 39o-39q, n TR40o-40q, a TR41, etc. and an inverters of p TR42 and 43 and n TR44 and 45 to select a memory element among memory element connected in series. The 2nd row decoder is connected via a p TR46 which is controlled by a timing signal to a p TR47 forming the 3rd row decoder which is controlled via a block processing line 48. When the gating is performed with the timing signal between the separated 2nd row decoder and the line 48, just one row line 50 becomes active. As a result, a current flows only to a desired row line. Thus the current consumption is reduced, and a row decoder can be miniaturized with a simple constitution. |
